This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-357975, filed on Nov. 22, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to an analog switch circuit, which is especially used for CMOS circuits.
2. Related Background Art
Generally, an analog switch circuit is used to disconnect a bus line from functional elements or to connect the bus line to the functional elements. A typical analog switch circuit 80 shown in FIG. 9 includes a P-channel MOS transistor P1, and an N-channel MOS transistor N1, whose source and drain are connected to the source and the drain of the P-channel MOS transistor P1, respectively. A supply voltage VDD serving as a substrate bias is applied to a well or substrate where the transistor P1 is formed, while a ground potential serving as a substrate bias is applied to a well or substrate where the transistor N1 is formed. The sources of the transistors P1 and N1 are connected to an I/O terminal 60, and the drains of the transistors P1 and N1 are connected to an I/O terminal 65. A control signal G is inputted to the gate of the transistor N1, and an inverted signal GB obtained by inverting the control signal G is inputted to the gate of the transistor P1.
In the analog switch circuit 80 thus constituted, when the switch is in the disabled (OFF) state, and a voltage VIN exceeding the supply voltage VDD is applied to one of the I/O terminals 60 and 65, for example the I/O terminal 65, a current i flows in the forward direction through a parasitic PN diode 85 constituted by the drain of the P-channel transistor P1, to which the I/O terminal 65 is connected, and a well or substrate where the P-channel transistor P1 is formed, as shown in FIG. 10. This arises a problem in that the potential levels of the I/O terminals 60 and 65 vary depending on the ON/OFF states of the analog switch.
An analog switch circuit according to the first aspect of the present invention includes: a first input-output terminal and a second input-output terminal; an analog switch including a first P-channel MOS transistor, a source of which is connected to the first input-output terminal, and a drain of which is connected to the second input-output terminal, and a first N-channel MOS transistor, a source of which is connected to the first input-output terminal, a drain of which is connected the second input-output terminal, and a gate of which receives a control signal; a comparison circuit comparing potentials of the first input-output terminal and the second input-output terminal, and conveying a higher potential to a semiconductor substrate or a well where the first P-channel MOS transistor is formed; a first potential conveying section conveying a potential of the semiconductor substrate or the well where the first P-channel MOS transistor is formed to a gate of the first P-channel MOS transistor when the analog switch is in an OFF state; a second potential conveying section operating based on the control signal to convey the potential of the semiconductor substrate or the well where the first P-channel MOS transistor is formed to the gate of the first P-channel MOS transistor to turn off the first P-channel MOS transistor; and a third potential conveying section operating based on the control signal to turn on the first P-channel MOS transistor.
An analog switch circuit according to the second aspect of the present invention includes: a first input-output terminal and a second input-output terminal; an analog switch including a first P-channel MOS transistor, a source of which is connected to the first input-output terminal, a drain of which is connected to the second input-output terminal, and a gate of which receives a control signal, and a first N-channel MOS transistor, a source of which is connected to the first input-output terminal, and a drain of which is connected the second input-output terminal; a comparison circuit comparing potentials of the first input-output terminal and the second input-output terminal, and conveying a higher potential to a semiconductor substrate or a well where the first N-channel MOS transistor is formed; a first potential conveying section conveying a potential of the semiconductor substrate or the well where the first N-channel MOS transistor is formed to a gate of the first N-channel MOS transistor when the analog switch is in an OFF state; a second potential conveying section operating based on the control signal to convey the potential of the semiconductor substrate or the well where the first N-channel MOS transistor is formed to the gate of the first N-channel MOS transistor to turn off the first N-channel MOS transistor; and a third potential conveying section operating based on the control signal to turn on the first N-channel MOS transistor.